1. Field of the Invention
The present invention pertains to memories and memory testing. More particularly, this invention relates to software controlled timing of embedded memory.
2. Background
Continual advances in processor technology have led to continual increases in the functionality provided in a single processor chip. One example of such functionality is on-chip memories, often referred to as cache memories. On-chip cache memories provide storage of data and/or instructions as well as various other control and/or address information for use by the execution unit(s) and other internal logic of the processor. These on-chip cache memories are typically very fast memories, with the combination of their speed as well as their close physical locality to the execution unit(s) and other internal logic leading to fast memory accesses for the information stored in these memories.
However, the fabrication of memories does not produce perfect results and, therefore, processors will occasionally be fabricated which have faulty memories. The faults may be complete failure of the memory cells, failure of particular cells, failure only under certain circumstances, failure of connections between cells, failure of controlling circuits, etc. Therefore, given that processors with such faulty memories may be fabricated, it would be beneficial to provide a way to test the embedded memories to verify their performance. Unfortunately, given the embedded nature of these memories, it is typically not possible to easily alter the timing of control signals for accessing the memory from external to the processor, thereby making testing very difficult. Thus, the identification of the faulty part of the memory, as well as which control signals, if any, are contributing to the fault is difficult to detect.
Additionally, strict timing requirements for signals accessing memories leaves very little room for design flaws. Therefore, it is similarly important to designers to be able to easily analyze and evaluate designs for flaws, allowing the designers to quickly and accurately finalize the design of a chip.
Furthermore, in typical prior art systems even if a particular control signal can be identified as causing an improper result there is typically no way to programmably alter the timing of that signal to any precise degree on the chip. Typical solutions are to alter the timing of the control signal by changing the circuitry on the chip (e.g., adding or removing gate delays, capacitance, etc.) and fabricate a new chip with the altered timing. Such solutions, however, are expensive and can be very time consuming, especially if multiple iterations are necessary.
Thus, a need exists for improved testing of embedded memories.
A method and apparatus for software controlled timing of embedded memory is described herein. An apparatus is disclosed including an embedded memory array and input/output (I/O) control circuitry coupled to the embedded memory array. The I/O control circuitry provides a plurality of I/O signals to the embedded memory array to control the input of data to the embedded memory array and output of data from the embedded memory array. The I/O control circuitry also includes programmable delay circuitry to alter the timing of the I/O signals.
A method is disclosed including providing a plurality of input/output (I/O) signals to I/O circuitry associated with an embedded memory array. Additionally, the timing of one or more of the plurality of I/O signals is programmably altered to alter the delay of the one or more I/O signals.